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Prof. Jae W. Han (Yonsei University) |
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EUV pellicle with 30 years of lithography life Prof. Hye-Keun Oh (Hanyang University) It has been more than 30 years since I began the lithography career at Hyundai Electronics. Electron beam was my first assignment, followed by PSM and OAI. My lifetime fortune began with this lithography experience and I could continue wonderful lithography career after I moved to Hanyang University with good personal relationships with good people. I remember a pleasant hiking with Deogbae Kim at 193 Symp (1995-2000) in Colorado Springs, Co, a dinner with Hyeongsu Kim at 157 Symp (2001-2002) in San Diego, CA, long discussion with Jonhwook Geh at Immersion Symp (2004-2009) in Keystone, Co, and shared a motel room with Jinho Ahn at 1st EUV Symp (2002-2020) in Dallas, TX and had a good time with Changmoon Lim at Lake Tahoe, CA, 2008, and drank beer at Miami Beach with Hanku Cho 2011. Sangho Lee helped me to host 1st Korean get-together party at 1992(1994?) SPIE Lithography Conf. Kiho Baik and Woosung Han joined me to open Korean Lithographers Workshop in Korea. Seongsue Kim had been a leader for 10-year long Korean EUV Initiative. EUV source, resist, mask, and defect control have been key issues to be a main player in current and future generations of semiconductor devices. Many blocks are cleared, even though some need more work. More power source, better sensitive resist, and less defect on mask are still needed for mass production and high yield. EUV pellicle is the first wish to have in our hands. However, EUV absorption in material prevents to have a commercial EUV pellicle. An EUV pellicle should be thin enough to transmit the light and be strong enough not to be broken. It is known that mask in-and-out and particle bombardment are key reasons to destroy and reduce the pellicle lifetime. Decision to make to-go or not-to-go for an on-going pellicle will be a game changer in COO. Experience
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Extending semiconductor patterning into the next decade Dr. Michael Lercel (Sr. Director Strategic Marketing, ASML) Scaling has enabled the semiconductor industry to be vibrant and growing for decades. Current market drivers continue to show a current and future strong demand for semiconductors. So the long term industry outlook is good – can technology keep up? Advanced patterning is dependent on having the right lithography, process, and metrology tools. Printing small features is not enough – tight control of tolerances, good yield, and cycle time are essential for manufacturability. EUV is now positioned to enhance logic and memory processes with improved cycle time, less variability from multiple processes, and reduced process complexity compared to multiple patterning. Production with EUV is underway, so now the question becomes how does EUV enable the 3nm node and beyond. EUV layer adoption is anticipated to increase at 5nm logic node versus the 7nm logic node where it is being first introduced. The same benefits of reduced process complexity, shorter cycle time, and reduced variability are now expanded as an all-optical 5nm logic node would involve nearly 100 mask levels. Beyond the 5nm logic node, higher Numerical Aperture (NA) EUV will further extend EUV single exposure resolution to enable Moore’s law scaling to the 3nm node and beyond. In this presentation, we review the progress on enabling EUV for logic and memory manufacturing with progress on productivity, overlay performance, and availability of the EUV scanner plus the metrology and infrastructure progress to enable high-volume manufacturing. The extensions to enable EUV for 5nm node logic, and the preparation of high-NA EUV for 3nm and beyond node logic will be reviewed. Experience
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Biography Experience in many parts of semiconductor manufacturing with particular emphasis on lithography and patterning topics. Has worked on many “next generation lithography” techniques – including first EUV work in 1998. PhD in physics from Cornell University in using ebeam lithography on monomolecular self-assembled films. Currently working on corporate strategy, product portfolio, and (as always) customer impact |
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3 decades in lithography – the ever moving brick wall Dr. Bernd Geh (Senior Principal Scientist, Carl-Zeiss) The year 2019 marked both the 50th anniversary of the moon landing as well as the first year where EUV Lithography was introduced for High Volume Production and the past 2 years have clearly shown the success of this technology. ZEISS optics were involved in both cases. The author will take this opportunity to give an overview of the evolution of Lithography lenses over the last 3 decades - culminating in the development of EUV lenses being used today in ASML scanners and the High NA EUV lenses that will be available soon. In parallel, ever since the author was involved in Lithography, there were strong voices warning about the “brick wall”: A fundamental limitation for feature size that was predicted always to be “a few years ahead of the now” as will be shown in examples. While there is no doubt that shrink can’t go on forever, we always figured out how to work with the currently given limitations and there is good reason to assume that this will continue. An overview of the current status in EUV will be given as well as other ZEISS solutions to support the infra structure of the industry. |
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Biography Bernd Geh is a Senior Principle Scientist at Carl Zeiss SMT. He received his masters degree in physics (Dipl. Phys.) from the University of Munich (1987). In 1988 he joined Carl Zeiss. He worked at Zeiss corporate research and in the interferometry division until he joined the Metrology Department of the Zeiss Semiconductor Optics Division in 1995. Since 2001 Bernd is a permanent Carl Zeiss assignee at the Technology Development Center at ASML in Chandler, AZ. He was elected SPIE Fellow in 2015. |
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Contacts: contact@ngl.or.kr |
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